This popular and recognized training event belongs to the series of VI-HPS Tuning Workshops, where around 30 participants receive instructions and guidance applying VI-HPS tools, e.g. Score-P, Scalasca or Vampir, to their own parallel application codes, along with advice for potential corrections and optimizations. The trainers, mostly developers of the VI-HPS tools, will give an overview of the VI-HPS programming tools suite, explain the functionality of individual tools, and how to use them effectively, offer hands-on experience and expert assistance…

In order to increase the efficiency of our users' applications on Hazel Hen, HLRS and Cray offer this workshop to enhance the node-level performance as well as scaling of the codes utilized by participants. By doing so, users can raise the volume as well as quality of their scientific findings while the costs (in terms of core hours) remain constant. Language: German (in English, if required) Deadline for registration is Mar. 25, 2018 Fee: Members of German universities and public…

The focus of this 2 days course is on shared memory parallelization with OpenMP for dual-core, multi-core, shared memory, and ccNUMA platforms. This course teaches OpenMP starting from a beginners level. Hands-on sessions (in C and Fortran) will allow users to immediately test and understand the OpenMP directives, environment variables, and library routines. Race-condition debugging tools are also presented. This course is organized by the Vienna Scientific Cluster (VSC), TU Wien in cooperation with HLRS. It is based on the…

On clusters and distributed memory architectures, parallel programming with the Message Passing Interface (MPI) is the dominating programming model. This 3 days course teaches parallel programming with MPI starting from a beginners level. Hands-on sessions (in C and Fortran) will allow users to immediately test and understand the basic constructs of the Message Passing Interface (MPI). This course is organized by the Vienna Scientific Cluster (VSC), TU Wien in cooperation with HLRS. It is based on the HLRS MPI course.…

The 41st International ICT Convention MIPRO 2018 is traditionally dedicated to information and communication technology, electronics, microelectronics, renewable energy sources, ecology along with a new and high technologies in general.  

European HPC Summit Week 2018 in Ljubljana will gather main HPC stakeholders in Europe. Similar to previous years also this edition will offer a wide variety of workshops covering a number of application areas where supercomputers are key, as well as HPC technologies and infrastructures. European HPC Summit Week also offers a great opportunity to network with all relevant European HPC stakeholders, from technology suppliers and HPC infrastructures to scientific and industrial HPC users in Europe. The registration fee for…

Most HPC systems are clusters of shared memory nodes. Such SMP nodes can be small multi-core CPUs up to large many-core CPUs. Parallel programming may combine the distributed memory parallelization on the node interconnect (e.g., with the Message Passing Interface - MPI) with the shared memory parallelization inside of each node (e.g., with OpenMP or MPI-3.0 shared memory). This course analyses the strengths and weaknesses of several parallel programming models on clusters of SMP nodes. Tools for hybrid programming such…

This course teaches performance engineering approaches on the compute node level. "Performance engineering" as we define it is more than employing tools to identify hotspots and bottlenecks. It is about developing a thorough understanding of the interactions between software and hardware. This process must start at the core, socket, and node level, where the code gets executed that does the actual computational work. Once the architectural requirements of a code are understood and correlated with performance measurements, the potential benefit…